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GS1574 HD-LINX TM II Adaptive Cable Equalizer
GS1574 Preliminary Data Sheet Features
* * * * * * * * * * * * * * SMPTE 292M, SMPTE 344M and SMPTE 259M compliant Automatic cable equalization Multi-standard operation from 143Mb/s to 1.485Gb/s Supports DVB-ASI at 270Mb/s Small footprint (4mm x 4mm) Pb-free and Green Pin compatible with the GS9074 Cable Equalizer Manual bypass (useful for low data rates with slow rise/fall times) Performance optimized for 270Mb/s and 1.485Gb/s Typical maximum equalized length of Belden 1694A cable: 140m at 1.485Gb/s, 350m at 270Mb/s 50 differential output (with internal 50 pull-ups) Manual output mute or programmable mute based on max cable length adjust Single 3.3V power supply operation Operating temperature range: 0C to +70C
Description The GS1574 is a second-generation high-speed bipolar integrated circuit designed to equalize and restore signals received over 75 co-axial cable. The GS1574 is designed to support SMPTE 292M, SMPTE 344M and SMPTE 259M, and is optimized for performance at 270Mb/s and 1.485Gb/s. The GS1574 features DC restoration to compensate for the DC content of SMPTE pathological test patterns. A voltage programmable mute threshold (MCLADJ) is included to allow muting of the GS1574 output when an approximate selected cable length is reached for SMPTE 259M signals. This feature allows the GS1574 to distinguish between low amplitude SD-SDI signals and noise at the input of the device. The serial digital outputs of the GS1574 may be forced to a mute state by applying a voltage to the MUTE pin. Power consumption is typically 270mW using a 3.3V power supply. The GS1574 is lead-free, and the encapsulation compound does not contain halogenated flame retardant.
Applications
* SMPTE 292M, SMPTE 344M and SMPTE 259M Coaxial Cable Serial Digital Interfaces.
MCLADJ
CABLE LENGTH ADJUSTOR CARRIER DETECT MUTE
MUTE
BYPASS SDI SDI SDO SDO
EQUALIZER
DC RESTORE
OUTPUT
AGC
GS1574 Functional Block Diagram
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GS1574 Preliminary Data Sheet
Contents
Features ........................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................3 1.1 GS1574 Pin Assignment .................................................................................3 1.2 GS1574 Pin Descriptions ................................................................................4 2. Electrical Characteristics ...........................................................................................5 2.1 Absolute Maximum Ratings ............................................................................5 2.2 DC Electrical Characteristics ..........................................................................5 2.3 AC Electrical Characteristics ...........................................................................6 2.4 Solder Reflow Profiles .....................................................................................7 3. Input / Output Circuits ...............................................................................................9 4. Detailed Description ................................................................................................11 4.1 Serial Digital Inputs .......................................................................................11 4.2 Cable Equalization ........................................................................................11 4.3 Programmable Mute Output ..........................................................................12 4.4 Mute ..............................................................................................................12 5. Application Information............................................................................................13 5.1 PCB Layout ...................................................................................................13 5.2 Typical Application Circuit A .........................................................................13 5.3 Typical Application Circuit B .........................................................................14 6. Package & Ordering Information .............................................................................15 6.1 Package Dimensions ....................................................................................15 6.2 Land Information ...........................................................................................16 6.3 Packaging Data .............................................................................................16 6.4 Ordering Information .....................................................................................16 7. Revision History ......................................................................................................17
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GS1574 Preliminary Data Sheet
1. Pin Out
1.1 GS1574 Pin Assignment
VCC_A MUTE VCC_D
13 12 VEE_D 11 GS1574 (top view) SDI 3 10 SDO
16 VEE_A 1
15
NC
14
SDI
2
SDO
VEE_A
4 5 6 7 8
9
VEE_D
BYPASS
Figure 1-1: 16-Pin QFN
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MCLADJ
Center Pad (bottom of package, internally bonded to VEE_A)
AGC
AGC
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GS1574 Preliminary Data Sheet
1.2 GS1574 Pin Descriptions
Table 1-1: GS1574 Pin Descriptions Pin Number
1, 4
Name
VEE_A
Timing
Analog
Type
Power
Description
Most negative power supply for analog circuitry. Connect to analog GND.
2, 3 5, 6
SDI, SDI AGC, AGC
Analog Analog
Input -
Serial digital differential input. External AGC capacitor. Connect pin 5 and pin 6 together through a 1uF capacitor.
7 8
BYPASS MCLADJ
Not Synchronous Analog
Input Input
Forces the Equalizing and DC RESTORE stages into bypass mode when HIGH. No equalization occurs in this mode. Maximum cable length adjust. Adjusts the approximate maximum amount of cable to be equalized (from 0m to the maximum cable length). The output is muted (latched to the last state) when the maximum cable length is achieved. NOTE: MCLADJ is only recommended for data rates up to 360Mb/s.
9
VEE_D
Analog
Power
Most negative power supply for the digital circuitry and output buffer. Connect to digital GND.
10, 11 12
SDO, SDO VEE_D
Analog Analog
Output Power
Equalized serial digital differential output. Most negative power supply for the digital circuitry and output buffer. Connect to digital GND.
13
VCC_D
Analog
Power
Most positive power supply for the digital I/O pins of the device. Connect to +3.3V DC.
14
MUTE
Not Synchronous
Input
CONTROL SIGNAL INPUT levels are LVCMOS/LVTTL compatible. (3.3V Tolerant) When the MUTE pin is set HIGH by the application interface, the serial digital output of the device will be forced to a steady state. When the MUTE pin is set LOW, the serial digital output of the device will be active.
15 16
NC VCC_A
- Analog
- Power
No Connect. Most positive power supply for the analog circuitry of the device. Connect to +3.3V DC.
-
Center Pad
-
Power
Internally bonded to VEE_A.
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GS1574 Preliminary Data Sheet
2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Supply Voltage Input ESD Voltage (Human Body Model) Storage Temperature Range Input Voltage Range (any input) Operating Temperature Range Power Dissipation Lead Temperature (soldering, 10 sec)
Value
-0.5V to +3.6 VDC 500V -50C < Ts < 125C -0.3 to (VCC +0.3)V 0C to 70C 300mW 260C
2.2 DC Electrical Characteristics
Table 2-1: DC Electrical Characteristics
VDD = 3.3V, TA = 0C to 70C, unless otherwise shown
Parameter
Supply Voltage Power Consumption Supply Current Output Common Mode Voltage Input Common Mode Voltage Floating MCLADJ DC Voltage MCLADJ Range Mute Input Voltage Required to Force Outputs to Mute Mute Input Voltage Required to Force Outputs Active
Symbol
VCC PD Is VCMOUT VCMIN - - VMute
Conditions
- TA = 25C TA = 25C TA = 25C TA = 25C 0m, TA = 25C TA = 25C Min to Mute
Min
3.135 - - - - - - 3.0
Typ
3.3 265 80 VCC - VSDO/2 1.75 1.3 0.69 -
Max
3.465 - - - - - - -
Units
V mW mA V V V V V
Test Levels
- 2 1 7 8 7 7 7
Notes
5% - - - - - - -
VMute
Max to Activate
-
-
2.0
V
7
-
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GS1574 Preliminary Data Sheet
2.3 AC Electrical Characteristics
Table 2-2: AC Electrical Characteristics
VDD = 3.3V, TA = 0C to 70C, unless otherwise shown
Parameter
Serial input data rate Input Voltage Swing Output Voltage Swing
Symbol
DRSDO VSDI VSDO - - - - -
Conditions
GS1574 TA =25C, differential 100 load, TA =25C, differential 270Mb/s, Belden 1694A, 0.2UI Output Jitter 270Mb/s, Belden 8281, 0.2UI Output Jitter 540Mb/s, Belden 8281, 0.2UI Output Jitter 1.485Gb/s, Belden 1694A, 0.25UI Output Jitter 1.485Gb/s, Belden 8281, 0.25UI Output Jitter 20% - 80% - - - - single ended single ended single ended
Min
143 720 -
Typ
- 800 750
Max
1485 950 -
Units
Mb/s mVp-p mVp-p m m m m m ps ps ps % dB k pF
Test Levels
6 2 1
Notes
- 1 -
Maximum Equalized Cable Length
- - - - - - - - - 15 - - - NOTES:
350 280 100 140 100 80 - - - - 1.64 1 50
- - - - - 220 30 30 10 - - - -
5 2 8 5 2 1 1 1 7 8 6 6 6
2 2 2 2 2 - - 1 - 3 - - -
Output Rise/Fall time Mismatch in rise/fall time Duty cycle distortion Overshoot Input Return Loss Input Resistance Input Capacitance Output Resistance TEST LEVELS
- - - - - - - -
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test.
1. 0m cable length. 2. Equalizer Pathological. 3. Tested on CB1574 board from 5MHz to 2GHz.
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GS1574 Preliminary Data Sheet
2.4 Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. The recommended standard eutectic reflow profile is shown in Figure 2-1. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-2.
Temperature 60-150 sec.
10-20 sec. 230C 220C 3C/sec max 183C 6C/sec max 150C
100C
25C Time 120 sec. max 6 min. max
Figure 2-1: Standard Eutectic Solder Reflow Profile (Pb-free package)
Temperature 60-150 sec.
20-40 sec. 260C 250C 3C/sec max 217C 6C/sec max
200C
150C
25C
Time 60-180 sec. max 8 min. max
Figure 2-2: Maximum Pb-free Solder Reflow Profile (Pb-free package)
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GS1574 Preliminary Data Sheet
GigaBERT 1400 EXT. CLOCK DATA CLOCK OUT OUT 50/75
8281 or 1694A CABLE IN GS1574 TEST BOARD OUT OUT CH. 1 CH. 2 TDS 820 EXT. TRIGGER
EXT. CLOCK 1.485GHz/270MHz
Figure 2-3: Test Circuit
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GS1574 Preliminary Data Sheet
3. Input / Output Circuits
3k SDI RC 3.6k
3k SDI 3.6k
Figure 3-1: Input Equivalent Circuit
VCC
12.0k + MCLADJ -
150
Figure 3-2: MCLADJ Equivalent Circuit
50
50
SDO
SDO
Figure 3-3: Output Circuit
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GS1574 Preliminary Data Sheet
VCC
7.5k OUTPUT STAGE MUTE CONTROL MUTE
Figure 3-4: MUTE Circuit
Bypass
Internal Reference
Figure 3-5: Bypass Circuit
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GS1574 Preliminary Data Sheet
4. Detailed Description
The GS1574 is a high speed bipolar IC designed to equalize serial digital signals. The GS1574 can equalize both HD and SD serial digital signals, and will typically equalize greater than 140m of Belden 1694A cable at 1.485Gb/s and 350m at 270Mb/s. The GS1574 is powered from a single +3.3V power supply and consumes approximately 270mW of power.
4.1 Serial Digital Inputs
The serial data signal may be connected to the input pins (SDI/SDI) in either a differential or single ended configuration. AC coupling of the inputs is recommended, as the SDI and SDI inputs are internally biased at approximately 1.8V.
4.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse of the cable loss characteristic. In addition, the variation of the frequency response with control voltage imitates the variation of the inverse cable loss characteristic with cable length. The edge energy of the equalized signal is monitored by a detector circuit which produces an error signal corresponding to the difference between the desired edge energy and the actual edge energy. This error signal is integrated by both an internal and an external AGC filter capacitor providing a steady control voltage for the gain stage. As the frequency response of the gain stage is automatically varied by the application of negative feedback, the edge energy of the equalized signal is kept at a constant level which is representative of the original edge energy at the transmitter. The equalized signal is also DC restored, effectively restoring the logic threshold of the equalized signal to its correct level independent of shifts due to AC coupling. The digital output signals have a nominal voltage of 750mVpp differential, or 375mVpp single ended when terminated with 50 as shown in Figure 4-1.
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GS1574 Preliminary Data Sheet
+187.5mV VCM = 2.925V typical SDO -187.5mV
SDO 50 50
+187.5mV VCM = 2.925V typical -187.5mV
Figure 4-1: Typical Output Voltage Levels
4.3 Programmable Mute Output
For SMPTE 259M inputs, the GS1574 incorporates a programmable threshold output mute (MCLADJ). In applications where there are multiple input channels using the GS1574, it is advantageous to have a programmable mute output to avoid signal crosstalk. The output of the GS1574 can be muted when the input signal decreases below a certain input level. This threshold is determined using the input voltage applied to the MCLADJ pin. The MCLADJ pin may be left unconnected for applications where output muting is not required. This feature has been designed for use in applications such as routers where signal crosstalk and circuit noise cause the equalizer to output erroneous data when no input signal is present. The use of a Carrier Detect function with a fixed internal reference does not solve this problem since the signal to noise ratio on the circuit board could be significantly less than the default signal detection level set by the on chip reference. NOTE: MCLADJ is only recommended for data rates up to 360Mb/s.
4.4 Mute
In addition to the programmable mute output, the GS1574 includes a MUTE input pin that allows the application interface to mute the serial digital output at any time. Set the MUTE pin HIGH to mute SDO and SDO.
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GS1574 Preliminary Data Sheet
5. Application Information
5.1 PCB Layout
Special attention must be paid to component layout when designing serial digital interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: * * * * PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to change in trace impedance. The PCB ground plane is removed under the GS1574 input components to minimize parasitic capacitance. The PCB ground plane is removed under the GS1574 output components to minimize parasitic capacitance. High speed traces are curved to minimize impedance changes.
5.2 Typical Application Circuit A
MUTE VCC_A VCC
16
15
14
13
VCC_A
VCC_D
NC
MUTE
10n SDI 6.4n 1 VEE_A 1u 75 1u 3 SDI 2 SDI
10n VEE_D 12 + 4u7
SDO
SDO GS1574 SDO
11
10
+ SDO
BYPASS
MCLADJ
4 75 37.5
VEE_A
VEE_D
9
4u7
AGC
AGC
5 + 1u
6
7
8 MCLADJ BYPASS
NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted.
Figure 5-1: GS1574 Typical Application Circuit
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GS1574 Preliminary Data Sheet
5.3 Typical Application Circuit B
This application circuit should be used for future compatibility with the GS1574A. This circuit will work with GS1574 as well as the GS1574A and is recommended for all new designs.
CD MUTE VCC_A VCC
16 VCC_A 10n SDI 6.4n 1 VEE_A 1u 75 1u 3 SDI 2 SDI
15 CD
14 MUTE
13 VCC_D 10n VEE_D 12 + 4u7
SDO
SDO GS1574A SDO BYPASS MCLADJ
11
10
+ SDO
4 75 37.5
VEE_A AGC AGC
VEE_D
9
4u7
5 * 470n
6
7
8 MCLADJ
* 470n BYPASS * Value subject to change.
NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted.
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GS1574 Preliminary Data Sheet
6. Package & Ordering Information
6.1 Package Dimensions
4.00
DATUM A
B
0.40+/-0.05
2.76+/-0.10
PIN 1 AREA
4.00
CENTER TAB
DETAIL B
2X 2X
0.15 C 0.15 C DATUM B 0.65 16X
0.20 REF
0.000.350.05 0.10 CAB 0.05 C
0.10 C 16X 0.08 C SEATING PLANE
0.90+/-0.10 +0.03 0.02-0.02
DATUM A OR B
0.65/2 TERMINAL TIP 0.65 DETAIL B SCALE:NTS
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2.76+/-0.10
GS1574 Preliminary Data Sheet
6.2 Land Information
0.35 0.65
0.55
3.70
2.75
CENTER PAD
NOTE: All dimensions are in millimeters. 2.75 3.70
The Center Pad should be connected to the most negative power supply plane for analog circuitry in the device (VEE_A) by a minimum of 5 vias. NOTE: Suggested dimensions only. Final dimensions should conform to customer design rules and process optimizations.
6.3 Packaging Data
Parameter
Package Type Package Drawing Reference Moisture Sensitivity Level Junction to Case Thermal Resistance, j-c Junction to Air Thermal Resistance, j-a (at zero airflow) Psi Pb-free and Green
Value
4mm x 4mm 16-pin QFN JEDEC M0220 3 31.0C/W 43.8C/W 11.0C/W Yes
6.4 Ordering Information
Part Number
GS1574-CNE3
Package
Pb-free 16-pin QFN
Temperature Range
0C to 70C
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GS1574 Preliminary Data Sheet
7. Revision History
Version
B 0
ECR
133285 134166
Date
March 2004 August 2004
Changes and/or Modifications
Updated AIN to include information on the GS9074. Upgrade to preliminary data sheet. Remove all information on the GS9074. Expand detailed description information. AC/DC parameters updated. Add Pb-free and conventional solder reflow profiles. Edit pin descriptions. Added packaging data section. Added Pad Layout information. Updated Packaging Dimensions diagram. Corrected minor typing errors. Added Typical Application Circuit section with application information for future drop-in compatibility with GS1574A part.
1
134891
November 2004
2
135370
December 2004
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice.
GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX TEL. +44 (0)1252 747 000 FAX +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright March 2004 Gennum Corporation. All rights reserved. Printed in Canada www.gennum.com Proprietary and Confidential 28854 - 2 17 December 2004 17 of 17

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